For those people who do simulations in Verilog or VHDL for ASICs or FPGA firmware design,
they tend to simulate the design using either an open source tool like Icarus Verilog
or a proprietary one, for example Mentor Graphics Modelsim.
I've recently run into many cases where a significant fraction of my FPGA firmware resides
in the control system, in particular when you have to do fairly complex calculations
to work out the phase relationship of clock systems, etc... While you can do this
in a dedicated soft processor in the fabric, it would be nice to keep this in the PC
connected to the FPGA board.
This module is a modification of an example I found of a Mentor Graphics Modelsim
FLI (Foreign Language Interface) module for simulating a UART using a socket. A very
nice example but my firmwares all have Gigabit Ethernet. So this one is
adapted to bridge a local UDP loopback connection to a Xilinx local link interface. It
takes data received / sent and makes it look as if it came from the tri-mode Ethernet MAC
on a Xilinx Virtex 5. Very handy for testing or bridging to real software applications.
Other people I know have done this using tun/tap as a kernel interface, but I think this
version is useful for testing as the Ethernet frame information that the firmware sees is self-contained.
To use it, just compile the module and put it in your LD_LIBRARY_PATH. Then include the VHDL file in the
src directory in your code as a component. Connect to an instance of it and you're done.
Note this is only for Linux users, but it can be modified to run in Windows.
v0.1 (06 Oct 2009)
Tested on Modelsim SE 6.3e
v0.2 (22 Oct 2009)
Improved buffering and packet loss handling
Download fli_udp.tar.gz
